PCI's designed to share IRQs. BUT...

Post #1,374 by Another Scott 7/10/01 10:13:14 PM Reply	PCI's designed to share IRQs. BUT... like most PC hardware, there are exceptions. Here's a good page with info on IRQ sharing on the PCI bus, with an emphasis on problems NICs can have. [link\|http://personal.bellsouth.net/sdf/h/b/hburgiss/dsl/survival/irq.htm\| [link\|http://personal.bellsouth.net/sdf/h/b/hburgiss/dsl/survival/irq.htm\|http://personal.bel...ival/irq.htm]] Basically, IIRC, the PCI bus is more sophisticated than the old ISA bus in that it can discrimiate between two devices raising the same interrupt signal. Edge- versus level-triggering seems to raise a flag with me. Check Google for more details... HTH. Cheers, Scott.
Post #1,382 by Ashton 7/10/01 10:43:36 PM Reply	Good crib sheet.. Thanks. Saved. Interesting re SBLive stealing an Irq for DOS use - about which Windoze is oblivious! Also noted my E-machine has modem in 1st PCI slot adjacent to AGP! but - works like charm. Good reminder too, to make sure I remembered to disable the secondary IDE and second floppy in BIOS in the new boxes. Now as to edge VS level- triggering (??) - fer us scope types that rings a bell, but also a bit sophisticated for a toy box I'd a thunk: that is, for it to reliably discriminate / flip - for one trigger-level setting VS a slightly different criterion. At a 100 - 200 MHz bus rate, say ! (If you find that ref, be curious how they Do that.) Thanx, A.
Post #1,384 by Another Scott 7/10/01 11:03:08 PM Reply	Edge versus Level triggering of interrupts... I misrememberd. ISA uses edge, PCI uses level. [link\|http://mailman.real-time.com/pipermail/linux-kernel/2001-March/023682.html\|Here's] a bit I found about it. I'm no expert on this stuff. There should be better info out there - especially on Intel's site. HTH. Cheers, Scott.
Post #1,390 by Ashton 7/11/01 1:05:13 AM Reply	See what you mean. Heh! an analog! e- problem.. If my reading between lines is close enough: What he's calling "edge" triggering is.. that sort of detector, commonly using a Schmitt Trigger circuit: a feedback device which enhances the risetime via.. yup pos feedback! to give a thus faster dV/dt as a trigger pulse. What he calls "level triggering" implies an intentionally 'slower" device which is not concerned with dV/dt so much as just "change state when V= x.yz V". Guess I'll poke around a bit; hard to see how same line from an "Irq detector" under s/w control - could parse the two - but it seems that the Vectra didn't.. too well. How'd ya find That!? (It's amazing the amount of stuff you can see with a real analog GHz scope on these boards - let alone decipher) A.

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