Among other things, I did the design on the 32-bit (virtual) addressing feature and all the (so called) micro-programming unique to the 360/67 (i.e. in addition to what was on 360/65). Just to be clear, this micro-programming controls the cycle by cycle processes of the CPU to implement the machine instructions as visible to an assembler programmer. Some people call it pico-programming. This is work on bare metal.

The 360/67 machine came about in a bit of a panic when both MIT and Bell Labs decided that no IBM S/360 machine would do and made a deal with GE in Phoenix (yes General Electric made computers then) for computer suitable for time sharing. The OS for the GE machine was going to be Multics. (Unix is a somewhat self-deprecating take off on the Multics name). Anyway, IBM wanted to head off other high tech defections to GE machines with the 360/67 machine and TSS as the OS.

I think you may be mixing up TSS (Time Sharing System) and CP-67 (CP - Control Program). They were different.

TSS was developed in the IBM's Kingston and Mohansic Labs (both in New York State) and was the official IBM OS product for the 360/67. On temporary assignment for a while, I wrote one supervisor module and helped in debugging and resolving software/hardware issues. As usual, hardware guys finish first.

CP-67 was done in Cambridge, MA (near MIT) and initially was not a "product" but more of a research project and a follow-up to software work with a 360/44, an experimental machine. Since it was selling more machines (360/67) than TSS, it did become a product eventually to run on the S/370's and renamed to VM/CMS. TSS on the other hand died off.

Nice to see that picture you've provided. It's 512 KB! (about half a million dollars just for memory) machine. The DAT (Dynamic Address Translator) box is swung out on the left at the rear of the CPU frame. Those were fun days!

Models S/360/65 and 67 used CROS - Capacitive Read Only Storage manufactured in Poughkeepsie, NY. The micro-code was on what was called bit planes. It looked like a printed circuit with gold plated "lands" and covered with a thin sheet of Mylar. The bit planes were carefully and precisely pressed against vertical sense lines on the CPU frame. In effect they were arrays of pairs of tiny capacitors. When a word lines were pulsed with current the sense lines would pick up positive or negative pulses depending on how the capacitor flags were attached. In some ways it's like core memory selection. There were 16 such bit planes, 8 on each side of the CPU. Each bit plane had 256 words of 101 bits, so it's a total of 4K such words. IIRC, these bits were organized into 13 fields which corresponded to the maximum number of simultaneous CPU operations one could do. One of these fields was the address of where to go next. Where to go next was sometime a clustered group of word addresses with the specific address depending on some conditions. There was for example a 64 way branch used in decoding the machine instruction op-code. There was a large variety of things to test in two-way, four-way, eight-way, branches.

The CROS, indeed the whole machine, cycled every 200 nanoseconds, i.e. 5 MHz about like the original PC! The 56 bit CPU adder with expedited carry propagation, used in executing parts of floating point operations, did not have much time to spare.

These machines did have a 8 byte (64 bit) memory bus.

You know, I admired a good CE. Putting in ECs (engineering changes) on machines, was humbling. I had difficulty not having a wire-wrap error in as few as 5 wires. It sure helped to have someone else double-check. Of course, my wiring was done in blue or red insulated "red flag" wire and not the offical yellow. CEs used to do hundreds of wire-wraps, "reaming pins"* and all without error.

I did volunteer to go to Australia to support a couple of machines for a year once, but IBM in it's wisdom decided to train a local.

* reaming was the process of cutting a "land", i.e. printed copper line on a circuit board connecting that pin to other pins.

**BOX and BLUKE take note.**

One of the things I did in those years is an RPQ (IBM TLA for Request for Price Quotation) for the Israeli Defense Force on a S/360/65. It was a special machine instruction called MVC Reversed. An MVC instruction is the Move Character which can move from 1 to 256 bytes from one place to another. The MVC Reversed instruction did that as well but it reversed the order of the character string in the process. Right to left reading of Hebrew was the motivation. Forgive me Allah, for I have sinned. :)

I bet you have one of those yellow handled wire strippers for SLT wiring work that looked like small needle nosed pliers. Engineers had to borrow those from CEs, the technician in our computer lab, or the guys on the manufacturing floor. All I have from those days is 360/67 reference card.

And I didn't know that CEs replaced cores in core memory. I remember seeing core planes being assembled in Kingston. Tedious work done by women.

Gosh, all those TLAs. Have not thought about them in a long time.

The [link|http://www.science.uva.nl/faculteit/museum/CoreMemory.html|Core memory] I remember seeing used cores about 2 mm outside diameter. I'm sure some were much smaller.

I also remember seeing some made of a ceramic bobbin with a metal tape wound on it. These were quite large ~5 mm and used to perform logic functions. These I saw during a summer job with Burroughs (which later merged with Sperry Rand) to form Unisys.